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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4070B gates Quadruple exclusive-OR gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple exclusive-OR gate DESCRIPTION The HEF4070B provides the positive quadruple exclusive-OR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. HEF4070B gates Fig.2 Pinning diagram. HEF4070BP(N): 14-lead DIL; plastic (SOT27-1) HEF4070BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4070BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.1 Functional diagram. Fig.3 Logic diagram (one gate). APPLICATION INFORMATION Some examples of applications for the HEF4070B are: * Logical comparators * Parity checkers and generators FAMILY DATA, IDD LIMITS category GATES See Family Specifications TRUTH TABLE I1 L H L H Note 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) I2 L L H H O1 L H H L January 1995 2 Philips Semiconductors Product specification Quadruple exclusive-OR gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays In On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL 85 35 30 75 30 25 60 30 20 60 30 20 175 75 55 150 65 50 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns 58 ns 24 ns 21 ns 48 ns 19 ns 17 ns 10 ns 9 ns 6 ns 10 ns 9 ns 6 ns + + + + + + + + + + + + SYMBOL TYP. MAX. HEF4070B gates TYPICAL EXTRAPOLATION FORMULA (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 1100 fi + (foCL) x VDD2 4900 fi + (foCL) x 14 400 fi + (foCL) x VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 |
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